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Macros</h2></td></tr>
<tr class="memitem:a3921ef6af4f5fd6a35cb5089ef85a22a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xscugic__hw_8h.html#a3921ef6af4f5fd6a35cb5089ef85a22a">XSCUGIC_INT_CFG_OFFSET_CALC</a>(InterruptID)&#160;&#160;&#160;((u32)<a class="el" href="group__scugic__v3__1.html#ga8c3e4a0e11aeeb05a7425826893a48b5">XSCUGIC_INT_CFG_OFFSET</a> + (((InterruptID)/16U) * 4U))</td></tr>
<tr class="separator:a3921ef6af4f5fd6a35cb5089ef85a22a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af5f397349cab91733882c9d388498d5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xscugic__hw_8h.html#af5f397349cab91733882c9d388498d5b">XSCUGIC_PRIORITY_OFFSET_CALC</a>(InterruptID)&#160;&#160;&#160;((u32)<a class="el" href="group__scugic__v3__1.html#ga4e103b71357ac53c890d8aebd3b80997">XSCUGIC_PRIORITY_OFFSET</a> + (((InterruptID)/4U) * 4U))</td></tr>
<tr class="separator:af5f397349cab91733882c9d388498d5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa2cf2e3acd2e8cf537c415276efa3a97"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xscugic__hw_8h.html#aa2cf2e3acd2e8cf537c415276efa3a97">XSCUGIC_SPI_TARGET_OFFSET_CALC</a>(InterruptID)&#160;&#160;&#160;((u32)<a class="el" href="group__scugic__v3__1.html#ga0ff09d2f6f8b9b89f847f756ee0ed408">XSCUGIC_SPI_TARGET_OFFSET</a> + (((InterruptID)/4U) * 4U))</td></tr>
<tr class="separator:aa2cf2e3acd2e8cf537c415276efa3a97"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a37b4c6eb0a94fe5e17b6ce5ddc021f5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xscugic__hw_8h.html#a37b4c6eb0a94fe5e17b6ce5ddc021f5b">XSCUGIC_EN_DIS_OFFSET_CALC</a>(Register,  InterruptID)&#160;&#160;&#160;((Register) + (((InterruptID)/32U) * 4U))</td></tr>
<tr class="separator:a37b4c6eb0a94fe5e17b6ce5ddc021f5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af5fb346faf5dff7820e4ce87c86f8eca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca">XScuGic_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;(Xil_In32((BaseAddress) + (RegOffset)))</td></tr>
<tr class="separator:af5fb346faf5dff7820e4ce87c86f8eca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a01c0f85e48858531c313ce22cbfd2dfa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))</td></tr>
<tr class="separator:a01c0f85e48858531c313ce22cbfd2dfa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4aff587a8fa5cd71c0714f45b5fb0d46"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xscugic__hw_8h.html#a4aff587a8fa5cd71c0714f45b5fb0d46">XScuGic_EnableIntr</a>(DistBaseAddress,  Int_Id)</td></tr>
<tr class="separator:a4aff587a8fa5cd71c0714f45b5fb0d46"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a04ed1a0a82b2c7418461f4d261ecb110"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xscugic__hw_8h.html#a04ed1a0a82b2c7418461f4d261ecb110">XScuGic_DisableIntr</a>(DistBaseAddress,  Int_Id)</td></tr>
<tr class="separator:a04ed1a0a82b2c7418461f4d261ecb110"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Distributor Interface Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Define the offsets from the base address for all Distributor registers of the interrupt controller, some registers may be reserved in the hardware device. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Distributor Enable Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Controls if the distributor response to external interrupt inputs. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Controller Type Register</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Implementor ID Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Implementor and revision information. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Security Registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Each bit controls the security level of an interrupt, either secure or non secure.</p>
<p>These registers can only be accessed using secure read and write. There are registers for each of the CPU interfaces at offset 0x080. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x084. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Enable Set Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is enabled.</p>
<p>Writing a 0 has no effect. Use the ENABLE_CLR register to set a bit to 0. There are registers for each of the CPU interfaces at offset 0x100. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x104. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Enable Clear Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is enabled.</p>
<p>Writing a 0 has no effect. Writing a 1 disables an interrupt and sets the corresponding bit to 0. There are registers for each of the CPU interfaces at offset 0x180. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x184. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Pending Set Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Each bit controls the Pending or Active and Pending state of an interrupt, a 0 is not pending, a 1 is pending.</p>
<p>Writing a 0 has no effect. Writing a 1 sets an interrupt to the pending state. There are registers for each of the CPU interfaces at offset 0x200. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x204. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Pending Clear Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Each bit can clear the Pending or Active and Pending state of an interrupt, a 0 is not pending, a 1 is pending.</p>
<p>Writing a 0 has no effect. Writing a 1 clears the pending state of an interrupt. There are registers for each of the CPU interfaces at offset 0x280. With up to 8 registers aliased to the same address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x284. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Active Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Each bit provides the Active status of an interrupt, a 0 is not Active, a 1 is Active.</p>
<p>This is a read only register. There are registers for each of the CPU interfaces at offset 0x300. With up to 8 registers aliased to each address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 32 of these registers staring at location 0x380. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Priority Level Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Each byte in a Priority Level Register sets the priority level of an interrupt.</p>
<p>Reading the register provides the priority level of an interrupt. There are registers for each of the CPU interfaces at offset 0x400 through 0x41C. With up to 8 registers aliased to each address. 0 is highest priority, 0xFF is lowest. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 255 of these registers staring at location 0x420. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">SPI Target Register 0x800-0x8FB</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Each byte references a separate SPI and programs which of the up to 8 CPU interfaces are sent a Pending interrupt.</p>
<p>There are registers for each of the CPU interfaces at offset 0x800 through 0x81C. With up to 8 registers aliased to each address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 255 of these registers staring at location 0x820.</p>
<p>This driver does not support multiple CPU interfaces. These are included for complete documentation. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Configuration Register 0xC00-0xCFC</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The interrupt configuration registers program an SFI to be active HIGH level sensitive or rising edge sensitive.</p>
<p>Each bit pair describes the configuration for an INT_ID. SFI Read Only b10 always PPI Read Only depending on how the PPIs are configured. b01 Active HIGH level sensitive b11 Rising edge sensitive SPI LSB is read only. b01 Active HIGH level sensitive b11 Rising edge sensitive/ There are registers for each of the CPU interfaces at offset 0xC00 through 0xC04. With up to 8 registers aliased to each address. A register set for the SPI interrupts is available to all CPU interfaces. There are up to 255 of these registers staring at location 0xC08. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">PPI Status Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Enables an external AMBA master to access the status of the PPI inputs.</p>
<p>A CPU can only read the status of its local PPI signals and cannot read the status for other CPUs. This register is aliased for each CPU interface. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">SPI Status Register 0xd04-0xd7C</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Enables an external AMBA master to access the status of the SPI inputs.</p>
<p>There are up to 63 registers if the maximum number of SPI inputs are configured. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">AHB Configuration Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Provides the status of the CFGBIGEND input signal and allows the endianess of the GIC to be set. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Software Triggered Interrupt Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Controls issueing of software interrupts. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">CPU Interface Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Define the offsets from the base address for all CPU registers of the interrupt controller, some registers may be reserved in the hardware device. </p>
</div></td></tr>
<tr class="memitem:ga8ca0e14be574b074b47ef33108794ca1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga8ca0e14be574b074b47ef33108794ca1">XSCUGIC_ALIAS_BIN_PT_OFFSET</a>&#160;&#160;&#160;0x0000001CU</td></tr>
<tr class="separator:ga8ca0e14be574b074b47ef33108794ca1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>CPU Interface Control register definitions All bits are defined here although some are not available in the non-secure mode. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Binary Point Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>&lt; All interrupts</p>
<p>Binary Point register definitions </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Acknowledge Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Interrupt Acknowledge register definitions Identifies the current Pending interrupt, and the CPU ID for software interrupts. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">End of Interrupt Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>End of Interrupt register definitions Allows the CPU to signal the GIC when it completes an interrupt service routine. </p>
</div></td></tr>
<tr><td colspan="2"><div class="groupHeader">Running Priority Register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Running Priority register definitions Identifies the interrupt priority level of the highest priority active interrupt. </p>
</div></td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga96bfe161e3b4e401f76f2b35df9fab86"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler</a> (void *DeviceId)</td></tr>
<tr class="separator:ga96bfe161e3b4e401f76f2b35df9fab86"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2cbf5d5ac5273e00c0b16bd33ad0707f"><td class="memItemLeft" align="right" valign="top">s32&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga2cbf5d5ac5273e00c0b16bd33ad0707f">XScuGic_DeviceInitialize</a> (u32 DeviceId)</td></tr>
<tr class="separator:ga2cbf5d5ac5273e00c0b16bd33ad0707f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga73f026dbb3a8f29b830fb0a64a42c4bf"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga73f026dbb3a8f29b830fb0a64a42c4bf">XScuGic_RegisterHandler</a> (u32 BaseAddress, s32 InterruptID, Xil_InterruptHandler Handler, void *CallBackRef)</td></tr>
<tr class="separator:ga73f026dbb3a8f29b830fb0a64a42c4bf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf58a00ee3c052d8aec17b179c86388c7"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#gaf58a00ee3c052d8aec17b179c86388c7">XScuGic_SetPriTrigTypeByDistAddr</a> (u32 DistBaseAddress, u32 Int_Id, u8 Priority, u8 Trigger)</td></tr>
<tr class="separator:gaf58a00ee3c052d8aec17b179c86388c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0c6a61acf2d5d030542c788a9aa42004"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__scugic__v3__1.html#ga0c6a61acf2d5d030542c788a9aa42004">XScuGic_GetPriTrigTypeByDistAddr</a> (u32 DistBaseAddress, u32 Int_Id, u8 *Priority, u8 *Trigger)</td></tr>
<tr class="separator:ga0c6a61acf2d5d030542c788a9aa42004"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a04ed1a0a82b2c7418461f4d261ecb110"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XScuGic_DisableIntr</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">DistBaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Int_Id&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>((DistBaseAddress), \</div>
<div class="line">                         <a class="code" href="group__scugic__v3__1.html#ga7a61a9bf8e0b229925a5ddbf763b414b">XSCUGIC_DISABLE_OFFSET</a> + (((Int_Id) / 32U) * 4U), \</div>
<div class="line">                         (0x00000001U &lt;&lt; ((Int_Id) % 32U)))</div>
<div class="ttc" id="xscugic__hw_8h_html_a01c0f85e48858531c313ce22cbfd2dfa"><div class="ttname"><a href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a></div><div class="ttdeci">#define XScuGic_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Write the given Intc register. </div><div class="ttdef"><b>Definition:</b> xscugic_hw.h:624</div></div>
<div class="ttc" id="group__scugic__v3__1_html_ga7a61a9bf8e0b229925a5ddbf763b414b"><div class="ttname"><a href="group__scugic__v3__1.html#ga7a61a9bf8e0b229925a5ddbf763b414b">XSCUGIC_DISABLE_OFFSET</a></div><div class="ttdeci">#define XSCUGIC_DISABLE_OFFSET</div><div class="ttdoc">Enable Clear Register. </div><div class="ttdef"><b>Definition:</b> xscugic_hw.h:130</div></div>
</div><!-- fragment -->
<p>Disable specific interrupt(s) in the interrupt controller. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DistBaseAddress</td><td>is the Distributor Register base address of the device </td></tr>
    <tr><td class="paramname">Int_Id</td><td>is the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xscugic__hw_8h.html#a04ed1a0a82b2c7418461f4d261ecb110" title="Disable specific interrupt(s) in the interrupt controller. ">XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)</a> </dd></dl>

</div>
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<a class="anchor" id="a37b4c6eb0a94fe5e17b6ce5ddc021f5b"></a>
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          <td class="memname">#define XSCUGIC_EN_DIS_OFFSET_CALC</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Register, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InterruptID&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;((Register) + (((InterruptID)/32U) * 4U))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Read the Interrupt Clear-Enable Register offset for an interrupt ID. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">Register</td><td>is the register offset for the clear/enable bank. </td></tr>
    <tr><td class="paramname">InterruptID</td><td>is the interrupt number.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the offset</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>

</div>
</div>
<a class="anchor" id="a4aff587a8fa5cd71c0714f45b5fb0d46"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XScuGic_EnableIntr</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">DistBaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Int_Id&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<b>Value:</b><div class="fragment"><div class="line"><a class="code" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a>((DistBaseAddress), \</div>
<div class="line">                         <a class="code" href="group__scugic__v3__1.html#ga7e39be0cb9e08f4c9231f76e685a76cc">XSCUGIC_ENABLE_SET_OFFSET</a> + (((Int_Id) / 32U) * 4U), \</div>
<div class="line">                         (0x00000001U &lt;&lt; ((Int_Id) % 32U)))</div>
<div class="ttc" id="group__scugic__v3__1_html_ga7e39be0cb9e08f4c9231f76e685a76cc"><div class="ttname"><a href="group__scugic__v3__1.html#ga7e39be0cb9e08f4c9231f76e685a76cc">XSCUGIC_ENABLE_SET_OFFSET</a></div><div class="ttdeci">#define XSCUGIC_ENABLE_SET_OFFSET</div><div class="ttdoc">Enable Set Register. </div><div class="ttdef"><b>Definition:</b> xscugic_hw.h:127</div></div>
<div class="ttc" id="xscugic__hw_8h_html_a01c0f85e48858531c313ce22cbfd2dfa"><div class="ttname"><a href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa">XScuGic_WriteReg</a></div><div class="ttdeci">#define XScuGic_WriteReg(BaseAddress, RegOffset, Data)</div><div class="ttdoc">Write the given Intc register. </div><div class="ttdef"><b>Definition:</b> xscugic_hw.h:624</div></div>
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<p>Enable specific interrupt(s) in the interrupt controller. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">DistBaseAddress</td><td>is the Distributor Register base address of the device </td></tr>
    <tr><td class="paramname">Int_Id</td><td>is the ID of the interrupt source and should be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xscugic__hw_8h.html#a4aff587a8fa5cd71c0714f45b5fb0d46" title="Enable specific interrupt(s) in the interrupt controller. ">XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)</a> </dd></dl>

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          <td class="memname">#define XSCUGIC_INT_CFG_OFFSET_CALC</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InterruptID</td><td>)</td>
          <td>&#160;&#160;&#160;((u32)<a class="el" href="group__scugic__v3__1.html#ga8c3e4a0e11aeeb05a7425826893a48b5">XSCUGIC_INT_CFG_OFFSET</a> + (((InterruptID)/16U) * 4U))</td>
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<p>&lt; CPU ID </p>
<p>Read the Interrupt Configuration Register offset for an interrupt id.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InterruptID</td><td>is the interrupt number.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the offset</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType()</a>, <a class="el" href="group__scugic__v3__1.html#ga0c6a61acf2d5d030542c788a9aa42004">XScuGic_GetPriTrigTypeByDistAddr()</a>, <a class="el" href="group__scugic__v3__1.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, and <a class="el" href="group__scugic__v3__1.html#gaf58a00ee3c052d8aec17b179c86388c7">XScuGic_SetPriTrigTypeByDistAddr()</a>.</p>

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          <td class="memname">#define XSCUGIC_PRIORITY_OFFSET_CALC</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InterruptID</td><td>)</td>
          <td>&#160;&#160;&#160;((u32)<a class="el" href="group__scugic__v3__1.html#ga4e103b71357ac53c890d8aebd3b80997">XSCUGIC_PRIORITY_OFFSET</a> + (((InterruptID)/4U) * 4U))</td>
        </tr>
      </table>
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<p>Read the Interrupt Priority Register offset for an interrupt id. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InterruptID</td><td>is the interrupt number.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the offset</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga6ed162180ffb45b082c2fbe23951ba13">XScuGic_GetPriorityTriggerType()</a>, <a class="el" href="group__scugic__v3__1.html#ga0c6a61acf2d5d030542c788a9aa42004">XScuGic_GetPriTrigTypeByDistAddr()</a>, <a class="el" href="group__scugic__v3__1.html#ga79abd6248cb578142e9c475f20dbeb06">XScuGic_SetPriorityTriggerType()</a>, and <a class="el" href="group__scugic__v3__1.html#gaf58a00ee3c052d8aec17b179c86388c7">XScuGic_SetPriTrigTypeByDistAddr()</a>.</p>

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          <td class="memname">#define XScuGic_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_In32((BaseAddress) + (RegOffset)))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Read the given Intc register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be read</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xscugic__hw_8h.html#af5fb346faf5dff7820e4ce87c86f8eca" title="Read the given Intc register. ">XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler()</a>, <a class="el" href="group__scugic__v3__1.html#ga0c6a61acf2d5d030542c788a9aa42004">XScuGic_GetPriTrigTypeByDistAddr()</a>, and <a class="el" href="group__scugic__v3__1.html#gaf58a00ee3c052d8aec17b179c86388c7">XScuGic_SetPriTrigTypeByDistAddr()</a>.</p>

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          <td class="memname">#define XSCUGIC_SPI_TARGET_OFFSET_CALC</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">InterruptID</td><td>)</td>
          <td>&#160;&#160;&#160;((u32)<a class="el" href="group__scugic__v3__1.html#ga0ff09d2f6f8b9b89f847f756ee0ed408">XSCUGIC_SPI_TARGET_OFFSET</a> + (((InterruptID)/4U) * 4U))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Read the SPI Target Register offset for an interrupt id. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">InterruptID</td><td>is the interrupt number.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the offset</dd></dl>
<dl class="section note"><dt>Note</dt><dd></dd></dl>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga40ef6d42e9520bb550163c3afd598980">XScuGic_InterruptMaptoCpu()</a>.</p>

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          <td class="memname">#define XScuGic_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Write the given Intc register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the device. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset to be written </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write to the register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xscugic__hw_8h.html#a01c0f85e48858531c313ce22cbfd2dfa" title="Write the given Intc register. ">XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="group__scugic__v3__1.html#ga96bfe161e3b4e401f76f2b35df9fab86">XScuGic_DeviceInterruptHandler()</a>, and <a class="el" href="group__scugic__v3__1.html#gaf58a00ee3c052d8aec17b179c86388c7">XScuGic_SetPriTrigTypeByDistAddr()</a>.</p>

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